Flash memory systems are well-known. In typical flash memory systems, a sense amplifier is used to read data from a flash memory cell.
FIG. 1 depicts a prior art sense amplifier 100. Sense amplifier 100 comprises selected flash memory cell 102, which is the cell to be read. Sense amplifier 100 also comprises reference flash memory cell 122, against which selected flash memory cell 102 is compared. PMOS transistors 104, 106, 124, and 126 and NMOS transistors 108, 110, 112, 128, and 130 are arranged as shown. PMOS transistor 104 is controlled by CASREF (column address sensing reference), PMOS 106 is controlled by SEN_B (sense amplifier enable, active low), NMOS transistors 108, 112, and 128 are controlled by ATD (address transition detection, which detects a change in the received address), and NMOS transistors 110 and 130 are controlled by YMUX (Y multiplexor) which activates a BL (bit line). Selected flash memory cell 102 receives WL (word line) and SL (source line), and reference memory cell 122 receives SL (source line). Comparator 130 receives two inputs that are directly related to the current drawn by selected flash memory cell 102 and reference memory cell 122, and the output SOUT is directly indicative of the data value stored in selected flash memory cell 102.
One drawback of prior art sense amplifier 100 is that a constant current is drawn by memory cell 102 and its associated circuitry, which results in significant power consumption. In addition, reference memory cell 122 and its associated circuitry typically are provided in a separate read bank than the read bank in which selected memory cell 102 is located, which requires a large die area and more power consumption for additional Y-decoding. Also, the CASREF signal also is sensitive to noise, and the CASREF circuit also consumes significant standby current.
FIGS. 2, 3A, and 3B depict improved sense amplifier 200 previously designed by Applicant, and which is described in China Patent Application 201511030454.4, filed on Dec. 31, 2015, and titled “Low Power Sense Amplifier for a Flash Memory System,” which is incorporated herein by reference.
With reference to FIG. 2, sense amplifier 200 comprises reference circuit 280 and read circuit 290.
Reference circuit 280 comprises reference memory cell 206, NMOS transistors 202, 204, and 220, PMOS transistor 212, reference bit line 208, level shifter 214, inverter 218, and NOR gate 216, all configured as shown. NMOS transistor 202 is controlled by ATD (address transition detection), NMOS transistor 204 is controlled by YMUX (Y multiplexor), and NMOS transistor 220 is controlled by a BIAS signal. NOR gate 216 receives ATD as one of its inputs.
Read circuit 290 comprises selected memory cell 236, NMOS transistors 232, 234, and 250, PMOS transistor 242, bit line 238, level shifter 244, inverter 248, and NOR gate 246, all configured as shown. NMOS transistor 232 is controlled by ATD (address transition detection), NMOS transistor 234 is controlled by YMUX (Y multiplexor), and NMOS transistor 250 is controlled by a BIAS signal. NOR gate 246 receives ATD as one of its inputs. Thus, reference circuit 280 and read circuit 290 are identical, except that reference circuit 280 comprises reference memory cell 206, and read circuit 290 comprises selected memory cell 236.
In operation, sense amplifier 200 works as follows. Prior to a read operation, the BIAS signal is high, which pulls the voltage at the output of inverters 218 and 248 to ground through NMOS transistors 220 and 250, which causes ROUT and SOUT to be high. At the beginning of a read operation, ATD goes high, which signifies a detection in the change of the address received by the memory system, which coincides with the beginning of a read operation. NMOS transistors 202 and 232 are turned on, as are NMOS transistors 204 and 234 by YMUX. This allows reference cell 206 and selected memory cell 236 to draw current. Concurrently, reference bit line 208 and bit line 238 will begin charging. BIAS also goes low at the beginning of the read operation. At this stage, PMOS transistors 212 and 242 are off, as the voltage on its gate will be high.
ATD will then go low, which shuts off NMOS transistors 202 and 232. Reference bit line 208 will begin discharging through reference cell 206. As it does so, the voltage of reference bit line 208 will decrease, and at some point will drop low enough (below VREF) such that PMOS transistor 212 turns on. This causes ROUT to drop to low. Meanwhile, bit line 238 also is discharging through selected memory cell 236. As it does so, the voltage of bit line 238 will decrease, and at some point will drop low enough (below VREF) such that PMOS transistor 242 turns on. This causes SOUT to drop to low. Once ROUT/SOUT drop to low, each sense amplifier has a local feedback (216, 218 or 246, 248) to cut off its bias current, which reduces the power consumption.
Essentially, there is a race condition between reference circuit 280 and read circuit 290. If selected memory cell 236 draws more current than reference cell 206 (which would be the case if selected memory cell 236 is storing a “1” value), then SOUT will drop to low before ROUT drops to low. But if selected memory cell 236 draws less current than reference cell 206 (which would be the case if selected memory cell 236 is storing a “0” value), then SOUT will drop to low after ROUT drops to low. Thus, the timing of SOUT and ROUT dropping to low indicates the value stored in selected memory cell 236.
SOUT and ROUT are input into timing comparison circuit 260, and the output is DOUT, which indicates the value stored in selected memory cell 236.
FIG. 3A depicts a first embodiment of timing comparison circuit 260. Here, timing comparison circuit 260 comprises flip-flop 310, with SOUT as the D input, ROUT as the active low clock CK, and DOUT as the output. When ROUT goes low before SOUT, then DOUT will output a “0,” indicating that selected memory cell 236 is storing a “0.” When ROUT goes low after SOUT, then DOUT will output a “1,” indicating that selected memory cell 236 is storing a “1.”
FIG. 3B depicts a second embodiment of timing comparison circuit 260, which comprises an R-S latch. Timing comparison circuit 260 comprises inverters 320 and 322 and NAND gates 324 and 326 configured as shown, with SOUT and ROUT as inputs, and DOUT as the output. When ROUT goes low before SOUT, then DOUT will output a “0,” indicating that selected memory cell 236 is storing a “0.” When ROUT goes low after SOUT, then DOUT will output a “1,” indicating that selected memory cell 236 is storing a “1.”
While the system of FIGS. 2, 3A, and 3B is an improvement over the prior art system of FIG. 1, the system of FIGS. 2, 3A, and 3B still consumes a significant amount of power during the pre-charge process for the reference bit line 208 and the selected bit line 238.
What is needed is an improved sense amplifier that reduces power consumption compared to the systems of FIGS. 1, 2, 3A, and 3B by reducing the power consumption during the pre-charge process for reference bit lines and selected bit lines.